8086 Microprocessor -Internal Architecture of 8086

  • It is a 16-bit µp.
  • 8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).
  • It can support up to 64K I/O ports.
  • It provides 14, 16 -bit registers.
  • It has multiplexed address and data bus AD0- AD15 and A16 – A19.
  • It requires single phase clock with 33% duty cycle to provide internal timing.
  • 8086 is designed to operate in two modes, Minimum and Maximum.
  • It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up instruction execution.
  • It requires +5V power supply.
  • A 40 pin dual in line package

 

Minimum and Maximum Modes:
• The minimum mode is selected by applying logic 1 to the MN / MX input pin. This is a single microprocessor configuration.
• The maximum mode is selected by applying logic 0 to the MN / MX input pin. This is a multi micro processors configuration.

 

pin-diagram-of-8086

signal-groups-of-8086

block-diagram-of-8086

Internal Architecture of 8086

    • 8086 has two blocks BIU and EU.
    • The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue.
    • EU executes instructions from the instruction system byte queue.
    • Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance.
    • BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.
    • EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.

 

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