Interrupt Driven Data Transfer

INTERRUPT I/O TRANSFER

This is a device initiated Microprocessor controlled I/O transfer. A Microprocessor may be communicating other time. In the case of CPU initiated polled I/O transfer. Polling of I/O service request flags monopolizes a significant amount of a microprocessor time. This reduces system through put the total useful information processed or communicated during a specified time period therefore, it is advantageous, in term of increasing throughput as well as reducing program complexity, if an I/O device demands service directly from the microprocessor.

 

Interrupts provide this capability essentially an interrupt is a subroutine call initiated by external hardware device and is asynchronous meaning it can be initiated at any time without reference to the system clock however, the response to an interrupt is directed or controlled by the Microprocessor. A simple structure that allows

 

a single device to interrupt a microprocessor is shown fig.

interrupt-io-transfer

 

When an I/O device requires service, it sets its interrupt request flip-flop. This flip-flop is functionally the same as the service request. F/F except that instead of its output being connected to an input port, it is connected to an interrupt pin of the microprocessor. Thus, the F/F stores the I/O devices interrupt request until it is acknowledged by the Microprocessor Since the interrupt request is asynchronous, it may occur at any point in a program’s execution. when an interrupt occurs, the execution of the current instruction is completed, the interrupt is acknowledged by the Microprocessor , and the control is transferred to a subroutine that services the interrupt .

 

when the Microprocessor responds to the interrupt;  the interrupt request F/F is cleared by a signal directly from the Microprocessor or by a device select pulse generated by the service subroutine. To resume program execution at the proper point when the I/O service subroutine is finished, the program counter is automatically saved before control is transferred to the service subroutine.

 

The service subroutine saves the contents of any registers it uses on the stack and restores the register’s contents before returning. The contents of the program counter, flag register, accumulator, and general purpose registers together represent the state of the microprocessor.

 

There are two types of interrupt input non-maskable and maskable.

When a logic signal is applied to a non maskable interrupt input, the Microprocessor is immediately interrupted. When a logic signal is applied to a maskable interrupt input, the Microprocessor is interrupted only if that particular input is enabled maskable interrupts are enable or disabled under program control.flip flop disabled an interrupt request is ignored by the Microprocessor .

 

A non-maskable interrupt input can be masked externally by an interrupt mask signal from an output port. The mask bit from an output port shown in figure gates the interrupt signal. If an instruction writes a 1 in the mask bit position, the interrupt is enabled if it writes a 0, it is disabled.

 

In response to an interrupt, the following operations occur:

  1. The processing of amount instruction of the main program is completed
  2. An interrupt instruction cycle is executed during which the program counter is saved and control is transferred to an appropriate memory location.
  3. The state of a Microprocessor is saved.
  4. 2f more than one I/O device is associated with the location transferred to, the highest priority device requesting an interrupt is identified.
  5.  A subroutine is executed which services the interruputi9ng I/O this subroutine clears the interrupt service request F/F if it was not cleared in step 2
  6. The saved state of the Microprocessor is restored
  7. Control is returned to the instruction that follows the interrupted instruction.

 

Each step requires a certain amount of time. The combined times for a given Microprocessor and external interrupt logic determine how quickly the Microprocessor responds to an I/O devices request for service.

 

the timing involved in servicing the single interrupt

(1) Latency time
(2) Interrupt m/c cycle time or BIMC time
(3) Saved states
(4) Time taken to identify the device
(5) Actual servicing
(6) Restore states
(7) Return to previous procession of main program

 

The time that elapses between the occurrence of the interrupt and the beginning of the execution of the interrupt handling subroutine is the response time, the sum of the times of steps (1) through (4)the difference between the total time that the Microprocessor is interrupted and the service subroutine is referred to as overhead interrupt structures with zero overhead allow greater throughput.

 

Latency time is the time between the occurrences of an interrupt request the beginning of the interrupt m/c cycle the interrupt signal must be valid for a time greater or equal to the interrupt set up time tINs, before the falling edge of CLK of the last state of the instruction cycle in order for the next m/c cycle to be an interrupt m/c cycle. for the 8085 the minimum value of tins is 160 n sec If the interrupt becomes valid précised, tins seconds before the beginning of the next m/c cycle, than that cycle is an interrupt cycle with a minimum latency time, t LATMIN=tins 2f ,

 

however the interrupt signal becomes valid just after this setup time, then it is not responded to until after the next instruction is executed. the provides a worst case latency time of tLATMAX =160 ns + 18T.

 

This relationship assumes there are no WAIT and states in the instruction cycle during which an interrupt request occurs. A further assumption is, of course, that the interrupt is enabled when the interrupt request occurs.

 
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