Digital Electronics - Resistors and Counters MCQs

In this section of Digital Logic Design – Digital Electronics – Resistors and Counters MCQs (Multiple Choice Questions and Answers),We have tried to cover the below lists of topics.All these MCQs will help you prepare for the various Competitive Exams and University Level Exams.

Shift Register,Shift-Left /Shift-Right MCQs.
Decoders,Encoders MCQs.
Multiplexers,Demultiplexer MCQss.
Counters-Ring Counter,Synchronous Up/Down Counter,Programmable Counter MCQs .

PRACTICE IT NOW TO SHARPEN YOUR CONCEPT AND KNOWLEDGE

1. The minimum number of flip flops required to construct a mod 64( divide by 64) ripple counter are

4 flip flops
6 flip flops
16 flip flops
64 flip flops

2. the maximum frequency to which Mod 16 ripple counter using 4 J-K flip flop with propagation delay time of 50 Nano second is

4 megahertz
5 megahertz
3.2 megahertz
320 megahertz

3. the type of register in which data is entered into it only one bit at a time, but has all data bits available as output, is

serial in serial out register
parallel in serial out register
serial in parallel out register
parallel in parallel out register

4. the type of register, in which we have access only to left most and right most flip flop is

shift left and shift right registers
serial in serial out register
parallel in serial out register
serial in parallel out register

5. the counter which requires maximum number of flip flop for a given Mod number is

ripple counter
BCD counter
ring counter
Programmable counter

6. Shifting a binary data to the left by 1 bit position using shift left register, amount 2

addition of two
subtraction of two
multiplication by 2
division by 2

7. if a counter is connected using 6 flip flop then the maximum number of states that the counter can count are

8. the minimum number of flip flop required for a mod 10 ripple counter are

9. the maximum modulo number that can be obtained by ripple counter using 5 flip flops is

10. Mod 5 synchronous counter is designed using J-K flip flops, the number of count skipped by it will be

11. the number of flip flops required for a mod 16 ring counter are

4 flip flops
8 flip flops
10 flip flops
16 flip flops

12. ABCD counter has

three distinct States
8 distinct States
10 distinct States
16 distinct States

13.
output frequency of decade counter, which is Clocked from 50 kilohertz signal is

5 KhZ
50 khz
500 khz
5000 khz

14. the output frequency of a Mod 16 counter, checked from a 10k Hz clock input signal is

10 khz
26khz
160khz
625khz

15. the table which shows the necessary levels at J and K input to produce every possible flip flop state transition is called

truth table of JK flip flop
excitation table of JK flip flop
excitation table of Mod n Counter using JK flip flop
none of these

EXAMRADAR

For Solo Learner Computer science

Digital Logic Design – Digital Electronics – Resistors and Counters MCQs

1. The minimum number of flip flops required to construct a mod 64( divide by 64) ripple counter are

2. the maximum frequency to which Mod 16 ripple counter using 4 J-K flip flop with propagation delay time of 50 Nano second is

3. the type of register in which data is entered into it only one bit at a time, but has all data bits available as output, is

4. the type of register, in which we have access only to left most and right most flip flop is

5. the counter which requires maximum number of flip flop for a given Mod number is

6. Shifting a binary data to the left by 1 bit position using shift left register, amount 2

7. if a counter is connected using 6 flip flop then the maximum number of states that the counter can count are

8. the minimum number of flip flop required for a mod 10 ripple counter are

9. the maximum modulo number that can be obtained by ripple counter using 5 flip flops is

10. Mod 5 synchronous counter is designed using J-K flip flops, the number of count skipped by it will be

11. the number of flip flops required for a mod 16 ring counter are

12. ABCD counter has

13.
output frequency of decade counter, which is Clocked from 50 kilohertz signal is

14. the output frequency of a Mod 16 counter, checked from a 10k Hz clock input signal is

15. the table which shows the necessary levels at J and K input to produce every possible flip flop state transition is called

You may be Interested In

Digital Logic Design – Digital Electronics – Resistors and Counters MCQs

1. The minimum number of flip flops required to construct a mod 64( divide by 64) ripple counter are

2. the maximum frequency to which Mod 16 ripple counter using 4 J-K flip flop with propagation delay time of 50 Nano second is

3. the type of register in which data is entered into it only one bit at a time, but has all data bits available as output, is

4. the type of register, in which we have access only to left most and right most flip flop is

5. the counter which requires maximum number of flip flop for a given Mod number is

6. Shifting a binary data to the left by 1 bit position using shift left register, amount 2

7. if a counter is connected using 6 flip flop then the maximum number of states that the counter can count are

8. the minimum number of flip flop required for a mod 10 ripple counter are

9. the maximum modulo number that can be obtained by ripple counter using 5 flip flops is

10. Mod 5 synchronous counter is designed using J-K flip flops, the number of count skipped by it will be

11. the number of flip flops required for a mod 16 ring counter are

12. ABCD counter has

13. output frequency of decade counter, which is Clocked from 50 kilohertz signal is

14. the output frequency of a Mod 16 counter, checked from a 10k Hz clock input signal is

15. the table which shows the necessary levels at J and K input to produce every possible flip flop state transition is called

You may be Interested In

13.
output frequency of decade counter, which is Clocked from 50 kilohertz signal is